This invention relates to a magnetic logic element and magnetic logic element array. More particularly, the invention relates to a magnetic logic element in which a recording of a direct-current-driving type and a reproduction by the magnetoresistance effect are possible, and a magnetic logic element array.
Since the discovery that giant magnetoresistance effect (MR) is exhibited when a current is supplied to flow in parallel with the major plane of a multi-layered structure, efforts have been paid to find systems having still larger magnetoresistance ratios. Heretofore, ferromagnetic tunnel junction elements and CPP (current-perpendicular-to-plane) type MR elements in which electric current flows vertically in a multi-layered structure have been developed and regarded hopeful as magnetic sensors and reproducing elements of for magnetic recording.
Recently, “magnetic nanocontacts” by tip-to-tip abutment of two nickel (Ni) needles and nanocontacts by contact of two magnetite elements were reported as elements exhibiting 100% or higher magnetoresistance effects in the literatures, (1) N. Garcia, M. Munoz and Y. W. Zhao, Physical Review Letters, vol.82, p2923 (1999) and (2) J. J. Versluijs, M. A. Bari and J. M. D. Coey, Physical Review Letters, vol. 87, p26601-1 (2001), respectively.
These magnetoresistance effect elements can be used not only as a reproduction element of a magnetic sensor or a magnetic record reproduction system, but also as an element of a non-volatile magnetic memory. However, these conventional elements functions only as a sensor or a memory.
On the other hand, a semiconductor device represented by silicon (Si) device is widely used not only as a memory device but as a logic circuit. However, these semiconductor circuit elements have small career concentration, and their resistance is essentially high. Therefore, integration increases power consumption. In addition, malfunction caused by downsizing also poses a problem. When using these semiconductor devices for a logic circuit, it is necessary to combine two or more transistors for one logic processing. Therefore, the further miniaturization is difficult.